The present invention relates to a semiconductor integrated circuit device comprising a non-volatile memory and a central processing unit. More particularly, the invention relates to techniques for providing a single-chip microcomputer, a data processing device, or a microprocessor which includes a flash memory and a central processing unit having a single external power supply.
Microcomputers incorporating a flash memory are known by the designations H8/538F, H8/3048 and H8/3434F, available from Hitachi, Ltd.
Memory cell transistors constituting a flash memory each have a floating gate, a control gate, a source and a drain. As such, each memory cell transistor retains binary information representing a charge injection state of its floating gate. For example, electrically charging the floating gate of a memory cell transistor brings a threshold voltage of that memory cell into a high state. When the threshold voltage is raised relative to the control gate, the memory cell prevents a current from flowing. Electrically discharging the floating gate of the memory cell lowers the threshold voltage with respect to the control gate, which allows the current to flow through the memory cell. Illustratively, bringing the threshold voltage of the memory cell higher than a word line selecting voltage level of a read state is called an erasure operation (providing a logical xe2x80x9c1xe2x80x9d which signifies an erasure state); while, bringing the threshold voltage of the memory cell lower than the word line selecting voltage level of the read state is called a programming operation (providing a logical xe2x80x9c0xe2x80x9d which signifies a programming state). Alternatively, the erasure state and the programming state may be defined inversely in terms of threshold voltage.
Writing or erasing data to or from memory cell transistors presupposes that their floating gates are placed in a high electric field as needed. This requires that the voltage for erasure or programming purposes be higher than the common power supply voltage, such as 3 V or 5 V. Such a high voltage is provided as an external power supply.
To obtain a high voltage externally requires that a high voltage generating circuit be mounted on the printed circuit board on which the microcomputer is assembled. To handle high voltages involves use of a specialized printed circuit board design that typically detracts from general usability.
The inventors of this invention investigated whether it was possible to use a single power supply, such as 3 V or 5 V, from which to operate a microcomputer incorporating a flash memory. The inventors"" experiments involved generating a high voltage for erasure and programming by internally boosting the voltage from a single external power supply.
Some manufacturers of microcomputers, conscious of today""s demand for lower power dissipation, have their devices operate on 3 V; while manufactureres of some systems design their products to operate from a single 5 V power supply. Whether to use a 3V or a 5 V power supply is determined according to the specifications of the system to which the microcomputer in question is applied. In this respect, it is in a semiconductor manufacturers"" interest to design microcomputers which are capable of operating with a relatively wide range of available power supplies, such as from 3 V to 5V.
With the above points taken into consideration, the inventors proceeded with their studies and brought to light some problems of the related art. There are two major charge injection methods for charging flash memories: a channel injection method and a tunnel current method. The channel injection method involves letting a relatively large current flow through the channel of a given memory cell transistor to generate hot electrons near the drain, whereby the floating gate is electrically charged. The tunnel current method involves allowing a tunneling current to flow through a relatively thin tunnel oxide (insulating) film near the drain by application of an electric field of a predetermined intensity between the floating gate and the drain, whereby electric charging is accomplished. The inventors have found that the channel that the channel injection method was not suitable for internal voltage boosting because of its need for a relatively large current. With the tunnel current method, on the other hand, simply effecting internal voltage boosting was found insufficient to implement programming and erasure of an internal flash memory in a stable manner within a relatively wide range of external power supply voltages, including those for low-voltage operations.
It is therefore an object of the present invention to provide a semiconductor integrated circuit device such as a microcomputer,including a non-volatile memory, such as a flash memory, which can be erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages, including those for low-voltage operations.
It is another object of the present invention to provide a semiconductor integrated circuit device such as a microcomputer,which incorporates a non-volatile memory, such as a flash memory, which is capable of being erased and programmed electrically and which offers higher usability than previously available.
Other objects, features and advantages of the present invention will become apparent from the description provided in the following specification with reference to the accompanying drawings.
In carrying out the invention and according to one aspect thereof, there is provided a semiconductor integrated circuit device, such as a microcomputer, comprising a semiconductor substrate incorporating a non-volatile memory, such as a flash memory, which is capable of being erased and programmed electrically, and a central processing unit which is capable of accessing the non-volatile memory. The semiconductor integrated circuit device operates on a single power supply voltage supplied to an external power supply terminal of the semiconductor substrate. The non-volatile memory includes: voltage clamp means which, using a reference voltage with a low dependency on a power supply voltage, clamps an output voltage to a first voltage lower in level than the single power supply voltage; boosting means for boosting the voltage output by the voltage clamp means to a positive and a negative high voltage; and a plurality of non-volatile memory cells which can be erased and programmed by use of the positive and negative high voltages output by the boosting means.
In the semiconductor integrated circuit device of the above constitution, the voltage clamp means generates a voltage that is negligibly dependent on a supply voltage. The voltage thus generated is clamped to a voltage level which, within a tolerable range of supply voltages for the semiconductor integrated circuit device, is lower than the single supply voltage externally furnished. The clamping prevents the voltages boosted by the boosting means operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage. This in turn makes it possible to erase and program the incorporated non volatile memory in a relatively wide range of externally supplied voltages,including those for low-voltage operations. Because these features are provided by use of a single external supply voltage, the semiconductor integrated circuit device incorporating the non-voltage memory is made easier and more convenient to use than before.
The efficiency of boosting may be enhanced by changing a substrate bias voltage common to MOS transistors (metal-oxide semiconductors; MIS or metal-insulating semiconductors may be used alternatively) carrying out charge pump operations when the boosted voltage has reached a predetermined level. Illustratively, the boosting means may include: a charge pump circuit having boosting nodes for negative high voltage generation, the boosting nodes being connected to p-channel MOS transistors and capacitors so as to implement a charge pump action for generating the negative high voltage; and switching means for switching halfway through a boosting operation the substrate bias voltage common to the MOS transistors from the output voltage of the voltage clamp means to a second voltage lower in level than the output voltage. The second voltage is higher in level than the boosted voltage in effect at a time of switching the voltages. In this example, a decline in the substrate bias voltage lowers the threshold voltage of the MOS transistors through what is known as the substrate bias effect. The lowered threshold voltage promotes the movement of electric charges through the MOS transistors executing charge pump operations. This in turn improves the efficiency of boosting operations and shortens the time it takes to reach a required boosted voltage.
The voltage being boosted by a charge pump operation fluctuates in amplitude in synchronism with the switching actions of the MOS transistors for charge pump operations. The resulting ripple effect may cause the substrate bias voltage to oscillate. Such oscillation is forestalled illustratively by the switching means possessing a hysteresis characteristic for maintaining the substrate bias voltage to the second voltage when the boosted voltage fluctuates in amplitude after the switching of the voltages. This kind of hysteresis characteristic may be acquired by use of a hysteresis comparator or an SR flip-flop circuit.
Where a plurality of charge pump circuits operate from a single power supply, instantaneous drops in the power supply voltage are minimized preferably by staggering the charge pump circuits in their operative phases. Illustratively, the boosting means may include: a negative volt-age boosting charge pump circuit having boosting nodes for negative high voltage generation, the boosting nodes being connected to MOS transistors and capacitors so as to implement a charge pump action for generating a negative high voltage, and a positive voltage boosting charge pump circuit having boosting nodes for positive high voltage generation, the boosting nodes being connected to MOS transistors and capacitors so as to implement a charge pump action for generating a positive high voltage In this setup, the MOS transistors in the positive voltage boosting charge pump may be arranged so as to differ in on-state phase from the MOS transistors in the negative voltage boosting charge pump.
Relatively large currents are needed to erase and program a non-volatile memory. For this reason, the power supply for a boosting circuit should not be connected directly to the power supplies for other circuits. In this respect, the voltage clamp means may preferably include: a reference voltage generating circuit for generating a reference voltage with a low dependency on a power supply voltage; a first constant voltage generating circuit for generating a voltage by placing an output circuit under control for negative feedback to the first voltage with respect to a reference voltage constituted by the reference voltage generated by the reference voltage generating circuit; and a second constant voltage generating circuit for generating a voltage by placing the output circuit under control for negative feedback to the first voltage with respect to a reference voltage constituted by the voltage output by the first constant voltage generating circuit. The voltage output by the second constant voltage generating circuit may be supplied to the positive and negative voltage boosting means.
The inventive semiconductor integrated circuit device may further comprise a third constant voltage generating circuit for generating a voltage by placing an output circuit under control for negative feedback with respect to a reference voltage constituted by the voltage output by the first constant voltage generating circuit. In this setup, the voltage output by the third constant voltage generating circuit may serve as a power supply voltage for use by a read system.
Variations in the voltage output by the voltage clamp means can result from differences between processes. To fine-adjust such output voltage variations, the voltage clamp means may preferably include: a trimming circuit; trimming control means for fine-adjusting the trimming circuit in accordance with trimming adjustment information; and register means set with the trimming adjustment information to be supplied to the trimming control means. The register means may receive the trimming adjustment information that is transferred from a specific region of the non-volatile memory. This arrangement allows the output voltage to be trimmed as desired by software. The arrangement steers clear of limitations on conventional setups which, once programmed, cannot be modified subsequently because of their use of fuses.
Where the trimming adjustment information is known to affect the read voltage for the non-volatile memory, the transfer of the trimming adjustment information from the non-volatile memory to the register means should preferably be carried out when a read operation on the memory is allowed to take longer than the predetermined time. This arrangement is desirable with a view toward preventing malfunctions. Specifically, the information transfer may be performed in synchronism with reset operations of the semiconductor integrated circuit device. This permits internal voltage fluctuations to settle within a reset operation before a trimming action is settled. After the reset, a read operation is carried out in a stable manner. Where the trimming adjustment information affects only the voltages for programming and erasure of the non-volatile memory, the transfer of the information may be carried out before a first vector fetch (instruction fetch) during the reset period or following the release of the reset state.
In view of the selection of trimming information the test mode, the central processing unit should preferably be capable of accessing the register means mentioned above.
Where the semiconductor integrated circuit device is programmed upon completion of a wafer (eg., logical xe2x80x9c0xe2x80x9d of a low threshold voltage) and is erased upon shipment (e.g., logical xe2x80x9c1xe2x80x9d of a high threshold voltage), it is desirable to minimize variations that may occur in the output voltage of the voltage clamp means as a result of the voltages being extremely trimmed between thee programming and the erasure states. The minimizing of such output voltage variations may be effected illustratively by the trimming control means including selective logic for determining trimming positions of the trimming circuit in accordance with the trimming adjustment information in such a manner that the trimming position in effect when the trimming adjustment information has an all-bit logic value of xe2x80x9c1xe2x80x9d is adjacent to the trimming position in effect when the trimming adjustment information has an all-bit logic value of xe2x80x9c0.xe2x80x9d In this setup, the voltage output by the voltage clamp means may be minimized in terms of difference between where the non-volatile memory is programmed upon completion of a wafer, and where the non-volatile memory is erased upon shipment.
It takes some time for the boosting means to gain a required boosted voltage. The required time is known to suffer from process-dependent variations. A programming and an erasure operation must each be started after the boosted voltage has reached a predetermined voltage level. These aspects are controlled by the central processing unit running suitable software. Illustratively, the inventive semiconductor integrated circuit device may comprise a control register for controlling the non-volatile memory, the control register including: a programming set-up bit for instructing the boosting means to start a boosting operation for programming; a programming enable bit for designating a start of a programming operation by use of the boosted voltage; an erasing set-up bit for instructing the boosting means to start a boosting operation for erasure; and an erasing enable bit for designating a start of an erasing operation by use of the boosted voltage. This arrangement eliminates the need for additionally providing hardware, such as a timer, for controlling when to start the actual erasing or programming the device after the erasure or the programming has been designated.
Furthermore, the control register may include a programming of enable bit for instructing the boosting means to prepare for a boosting operation, so that the instruction based on any of the erasing set-up bit and the programming set-up bit is accepted only if the programming enable bit is set to its true value. That is, a programming or erasure operation is carried out on condition that the programming enable bit be set to the true value. This arrangement helps prevent the non-volatile memory from getting inadvertently reprogrammed, for example, by a runaway central processing unit.
Inadvertent reprogramming of the non-volatile memory is prevented more reliably by the control register including a protect bit, for example, which is set in accordance with an external terminal status, so that the setting of the programming enable bit to the true value is enabled in an interlocking manner only if the protect bit is set to its true value.
In order to minimize loads exerted by the negative voltage for erasure or programming upon the internal circuits, it is desirable to connect the word lines and other related parts to a ground potential before applied voltages are changed. The object is achieved illustratively by a microcomputer comprising a semiconductor substrate incorporating a flash memory capable of being erased and programmed electrically and a central processing unit capable of accessing the flash memory, the microcomputer operating on a single power supply voltage supplied to an external power supply terminal of the semiconductor substrate. The flash memory may include: a memory cell array made of a plurality of memory cell transistors each having a control gate connected to a word line, a drain connected to a bit line, and a source line connected to a source line; a boosting circuit for generating a high voltage for programming and erasure on the memory cell transistors, an address decoder for generating a word line selection signal based on an address signal; a word driver circuit for establishing a word line selection level in effect upon a read operation as a first polarity with respect to the ground potential, the word driver circuit further establishing a word line selection level in effect upon a write operation as a second polarity with respect to the ground potential, and timing control means acting upon a start and an end of a write operation to force all word lines to the ground potential, to invert logically the polarity of the selection level for the word line selection signal for the address decoder, and to switch operating power supplies of the word driver.
These and other objects, features and advantages of the invention will become more apparent upon a reading of the following description and appended drawings.